In the fabrication of integrated circuits and other electronic devices, multiple layers of conducting, semiconducting and dielectric materials are deposited on or removed from a surface of a semiconductor wafer. Thin layers of conducting, semiconducting, and dielectric materials can be deposited by a number of deposition techniques. Common deposition techniques in modern processing include physical vapor deposition (PVD), also known as sputtering, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and electrochemical plating (ECP).
As layers of materials are sequentially deposited and removed, the uppermost surface of the wafer becomes non-planar. Because subsequent semiconductor processing (e.g., metallization) requires the wafer to have a flat surface, the wafer needs to be planarized. Planarization is useful in removing undesired surface topography and surface defects, such as rough surfaces, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials.
Chemical mechanical planarization, or chemical mechanical polishing (CMP), is a common technique used to planarize substrates, such as semiconductor wafers. In conventional CMP, a wafer is mounted on a carrier assembly and positioned in contact with a polishing pad in a CMP apparatus. The carrier assembly provides a controllable pressure to the wafer, pressing it against the polishing pad. The pad is moved (e.g., rotated) relative to the wafer by an external driving force. Simultaneously therewith, a polishing composition (“slurry”) or other polishing solution is provided between the wafer and the polishing pad. Thus, the wafer surface is polished and made planar by the chemical and mechanical action of the pad surface and slurry. However, there is a great deal of complexity involved in CMP. Each type of material requires a unique polishing composition, a properly designed polishing pad, optimized process settings for both polish and post-CMP clean and other factors that must be individually tailored to the application of polishing a particular material.
For advanced technical nodes, 10 nm and below, cobalt is being implemented to replace tungsten plugs connecting transistor gates to metal interconnects in Back End of Line (BEOL) and replace copper in metal lines and vias for the first few metal layers in BEOL. Cobalt will be deposited on top of Ti/TiN barrier layers in these schemes. All these new processes require CMP to achieve planarity to the desired targeted thickness and selectivity of materials.
For efficient performance the CMP industry requires cobalt slurry to deliver high cobalt removal rates of 1500 Å/min or greater and simultaneously demonstrate low barrier (for example TiN) removal rates for acceptable topographical control. Barrier layers separate conductive materials from non-conductive insulator dielectric materials such as TEOS and inhibit unwanted electro-migration from one layer to the next. Excessive barrier removal can result in electro-migration resulting in the semiconductor device mal-functioning. As the semiconductor industry is continually driven to improve chip performance by further miniaturization of devices the dimensions of the various materials becomes smaller and thinner and features on semiconductors become denser making CMP ever more challenging to provide the desired removal rates of metals such as cobalt and simultaneously prevent excessive removal of barrier layers and insulator materials to prevent mal-functioning of semiconductor devices.
Therefore, there is a need for a CMP polishing method and composition for cobalt which at least improves cobalt:TiN barrier removal rate selectivity.